Methods of forming through-silicon via structures including conductive protective layers

ABSTRACT

Through-Silicon-Via (TSV) structures can be provided by forming a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate, that is opposite the upper surface, and having a conductive protective layer comprising Ni and/or Co formed at a bottom of the conductive via. A polymer insulating layer can be formed on the backside surface that is separate from the substrate and in contact with the conductive protective layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.12/408,369, filed Mar. 20, 2009, which claims priority to Korean PatentApplication No. 2008-0080494, filed in the Korean Intellectual PropertyOffice on Aug. 18, 2008, the disclosures of which are incorporatedherein in their entirety by reference.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductors in general,and more particularly, to Through-Silicon-Via structures and methods offorming.

BACKGROUND

Advances in integration technology have led to the development of athree dimensionally stacked LSI approach taken in favor of theconventional two-dimensional LSI approach. Some types of threedimensional integration include package stacking, die stacking, andwafer stacking. Among the wafer stacking approach, a technique calledThrough-Silicon-Via (TSV) can be used to extend a via hole through asubstrate so that a conductive via may be formed that completelypenetrates the substrate. In turn, multiple substrates including TSVscan be stacked on one another to achieve three dimensional integration.In particular, the TSVs of different substrates can conduct signals fromone substrate to another without the use of, for example, wires.

Two approaches that can be used in the formation of TSVs include a “viafirst” approach and a “via last” approach. According to a via firstapproach, TSVs are formed through the substrate before a back end ofline process, for example, a metal interconnection process, isaccomplished. Furthermore, the via first approach may be used beforeCMOS devices are formed in the substrates. According to the via firstapproach, vias can be formed in the substrates to only partiallypenetrate the substrate wherein after the CMOS and back end of lineprocessing can be provided. Subsequently, the substrates can be thinnedso that the vias are exposed and bound together to achieve athree-dimensional stacked structure.

Alternatively, the TSVs can be formed after the formation of the CMOSdevices but before the back end of line processing. In particular, theCMOS devices can be formed on the substrate whereupon the vias can beformed to partially penetrate the substrate. Then, the back end of lineprocessing can be provided and followed by a thinning process tocomplete the TSVs. Finally, the substrates having the TSVs formedtherein can be bonded together to provide the three dimensionallystacked structure.

According to the via first approach, vias can be formed in the substrateeither before the CMOS devices are formed or before the back end of lineprocessing is provided. For example, the vias can be formed before theformation of CMOS devices by first forming vias that partially penetratethe substrate. Then, the C-MOS and back end of line processing can beprovided and followed by a thinning process, which can complete theformation of the TSVs and the substrate. Subsequently, multiplesubstrates including the TSVs can be bonded together to provide thethree dimensionally stacked structure.

According to the via last approach, the vias can be formed during orafter the back end of line processing (BEOL) or after a bonding process.When the TSVs are formed during the BEOL, the process can be referred toas a “TSV middle process.” Conventionally, the TSV middle process can beincluded in the TSV last process as well. For example, processes for theformation of layer in a CMOS process, such formation of ILD, metal 1TSV, and metal 2 processes.) For example, the via last approach can beused to provide TSVs after the back end of line processing, but beforebonding by forming CMOS devices and a back end of line processing beforethe formation of vias which partially penetrate the substrate.Subsequently, a thinning process can be used to complete the TSVstructure, which penetrates the substrate whereupon a bonding processcan be used to connect the substrates including the TSV structures toprovide the three dimensionally stacked structure.

Alternatively, the via last approach can be used to provide the TSVsafter the bonding. For example, the CMOS and back end of line processingcan be provided and followed by the bonding of separate wafers together.The bonding wafers can then be thinned to form the TSVs to provide thethree dimensionally stacked structure.

TSV structures are also discussed in, for example, the following U.S.patent documents: U.S. Pat. No. 6,916,725, U.S. Pat. No. 7,214,615, U.S.Pat. No. 7,282,444, and U.S. Patent Publication No. 2004/0245623.

SUMMARY

Embodiments according to the invention can provide methods of formingThrough-Silicon-Via (TSV) structures including forming a conductive viathrough a substrate extending from an upper surface of the substrate toa backside surface of the substrate, that is opposite the upper surface,and having a conductive protective layer comprising Ni and/or Co formedat a bottom of the conductive via. A polymer insulating layer can beformed on the backside surface that is separate from the substrate andin contact with the conductive protective layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view that illustrates Through-Silicon-Viastructures including conductive protective layers formed thereon in someembodiments according to the invention.

FIG. 2 is a flow chart that illustrates methods of formingThrough-Silicon-Via structures in some embodiments according to theinvention.

FIGS. 3-5 are cross sectional views that illustrate methods of formingTSV structures in some embodiments according to the invention.

FIG. 6 is a graph that illustrates the comparative diffusivity ofdifferent metals over a range of temperatures.

FIGS. 7-9 are cross sectional views that illustrate the formation of TSVstructures in some embodiments according to the invention.

FIGS. 10-12 are cross sectional views that illustrate the formation ofTSV structures in some embodiments according to the invention.

FIGS. 13-16 are cross sectional views that illustrate the formation ofTSV structures in some embodiments according to the invention.

FIG. 17 is a cross sectional view that illustrates TSV structuresincluding a groove formed on a contact pad in some embodiments accordingto the invention.

FIG. 18 is a cross sectional view that illustrates TSV structures havingan upper planar surface formed offset from a contact pad in someembodiments according to the invention.

FIGS. 19-22 are cross sectional views that illustrate the formation ofTSV structures in some embodiments according to the invention.

FIG. 23 is a cross sectional view that illustrates a schematicrepresentation of a stack of substrates including respective TSVstructures used to interconnect the substrates included in a packageconfigured for interconnection to an under lying structure using solderbumps in some embodiments according to the invention.

FIG. 24 is a cross sectional view that illustrates immediately adjacentsubstrates in the stack, electrically connected to one another byrespective TSV structures wherein at least one of the TSV structuresincludes a groove filled with solder to define a coplanar surface withan upper surface at the TSV structure having a groove formed therein insome embodiments according to the invention.

FIG. 25 is a cross sectional view that illustrates immediately adjacentsubstrates in a three dimensional stack electrically coupled to oneanother by respective TSV structures wherein at least one of thestructures includes a groove filled with solder that extends outside thegroove in some embodiments according to the invention.

FIG. 26 is a cross sectional view that illustrates immediately adjacentsubstrates in the three dimensional stack electrically connected to oneanother by respective TSV structures wherein solder is formed on theplanar surface of at least one of the TSV structures used toelectrically connect to the immediately adjacent TSV structure in someembodiments according to the invention.

FIG. 27 is a cross sectional schematic representation of a threedimensional stacked structure including TSVs in a zigzag patternutilizing contact pads offset from the TSV structures in someembodiments according to the invention.

FIG. 28 is a cross sectional schematic representation of a threedimensional stacked structure including TSV structures in an alignedpattern including contact pads formed within the TSV structures in someembodiments according to the invention.

FIG. 29 is a cross sectional schematic representation of a threedimensional structure including inverted TSV structures in someembodiments according to the invention.

FIG. 30 is a cross sectional view that illustrates the immediatelyadjacent substrates within three dimensional stack structure of FIG. 29wherein at least one of the TSV structures includes a groove thereinfilled with solder to define a planar surface of the TSV structureelectrically connected to the adjacent TSV structure in some embodimentsaccording to the invention.

FIG. 31 is a cross sectional view that illustrates immediately adjacentsubstrates within the three dimensionally stacked structures shown inFIG. 29 wherein the immediately adjacent TSV structures are electricallyconnected by solder therebetween formed one a planar surface of at leastone of the TSV structures in some embodiments according to theinvention.

FIG. 32 is a cross sectional schematic view that illustrates a threedimensionally stacked structure including TSV structures used tointerconnect substrates therein arranged to make a zigzag patternwherein the TSV structures include contact pads that are offset from theTSV structures in some embodiments according to the invention.

FIG. 33 is a plan schematic view of a standard form factor memory cardin some embodiments according to the invention.

FIG. 34 is a cross sectional view taken along the cross sectional lineI-I′ shown in FIG. 33 that illustrates a three dimensionally stackedstructure used to implement the memory card as part of the stack andfurther a controller chip associated therewith in some embodimentsaccording to the invention.

FIG. 35 is a plan view of a standard form factor memory card included ina three dimensionally stacked structure including TSV structures in someembodiments according to the invention.

FIG. 36 is a cross sectional schematic view taken along cross sectionalline II-II′ shown in FIG. 35 wherein a three dimensionally stackedstructure including TSV structures are used to implement non-volatilememory with TSV structures including contact pads formed therein used toelectrically connect the substrates in the stack to one another in someembodiments according to the invention.

FIG. 37 is schematic representation of a memory module including memorydevices with TSV structures therein in some embodiments according to theinvention.

FIG. 38 is a block diagram that illustrates an electronic systemincluding various devices including TSV structures in some embodimentsaccording to the invention.

DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions may beexaggerated for clarity. Like numbers refer to like elements throughout.As used herein the term “and/or” includes any and all combinations ofone or more of the associated listed items and may be abbreviated as“/”.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “having,” “having,” “includes,” and/or “including” whenused in this specification, specify the presence of stated features,regions, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer or region isreferred to as being “on” or extending “onto” another element (orvariations thereof), it can be directly on or extend directly onto theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” or extending“directly onto” another element (or variations thereof), there are nointervening elements present. It will also be understood that when anelement is referred to as being “connected” or “coupled” to anotherelement (or variations thereof), it can be directly connected or coupledto the other element or intervening elements may be present. Incontrast, when an element is referred to as being “directly connected”or “directly coupled” to another element (or variations thereof), thereare no intervening elements present.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, materials, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, material, region, layer or section fromanother element, material, region, layer or section. Thus, a firstelement, material, region, layer or section discussed below could betermed a second element, material, region, layer or section withoutdeparting from the teachings of the present invention.

Relative terms, such as “lower”, “back”, and “upper” may be used hereinto describe one element's relationship to another element as illustratedin the Figures. It will be understood that relative terms are intendedto encompass different orientations of the device in addition to theorientation depicted in the Figures. For example, if the structure inthe FIG. 1 is turned over, elements described as being on the “backside”of substrate would then be oriented on “upper” surface of the substrate.The exemplary term “upper”, can therefore, encompasses both anorientation of “lower” and “upper,” depending on the particularorientation of the figure. Similarly, if the structure in one of thefigures is turned over, elements described as “below” or “beneath” otherelements would then be oriented “above” the other elements. Theexemplary terms “below” or “beneath” can, therefore, encompass both anorientation of above and below.

Embodiments of the present invention are described herein with referenceto cross section and perspective illustrations that are schematicillustrations of idealized embodiments of the present invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the present invention should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, a region illustrated or described asflat may, typically, have rough and/or nonlinear features. Moreover,sharp angles that are illustrated, typically, may be rounded. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the precise shape of a region andare not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

FIG. 1 is a cross sectional view that illustrates a Through-Silicon-Via(TSV) structure 100 including a conductive via 105 that extends througha substrate 110 from an upper surface 111 to a back side surface 112. Itwill be understood that the terms “upper” and “back” sides are relativeterms used herein for convenience to differentiate one surface fromanother and, further, can be generally referred to the surfaces that areprocessed by thinning or etching to expose a protruding portion of theconductive via 105 as part of the completed TSV structure 100.

A conductive protective layer 115 is formed on the conductive via andextends on the side wall thereof to a bottom region of the conductivevia 105 proximate to the back side surface 112. A diffusion barrierlayer 525 is formed on the conductive protective layer 115 and extendsalong the side wall of the conductive via 105 but does not extend on tothe bottom region thereof. Still further, an insulating layer 120 isformed on the diffusion barrier layer 525 and also extends on the sidewall on the conductive via 105 and further, does not extend to thebottom region of the conductive via 105. It will be understood that insome embodiments according to the invention, the diffusion barrier layer525 and the insulating layer 120 can be combined into a single layer.

Still referring to FIG. 1 a separate polymer insulating layer 130 isformed on the back side surface 112 of the substrate 110 and extends onto the side walls of the conductive protective layer 115 proximate tothe conductive via 105. Furthermore, the outer surface of the separatepolymer insulating layer 130 has an inclined profile proximate to wherethe separate insulating layer 130 contacts the conductive protectivelayer 115.

In some embodiments according to the invention, the polymer insulatinglayer 130 has an average thickness, measure relative to the back sidesurface 112 at the conductive via that is greater than the thickness ofthe polymer insulating layer on the backside surface 112 spaced apartfrom the conductive via. In some embodiments according to the invention,the polymer insulating layer 130 is thinner on the conductive via sidewall than when measured relative to the back side surface. In stillother embodiments according to the invention, the polymer insulatinglayer 130 has a thickness of about 8 microns where the conductive via105 protrudes from the back side surface 112. In still other embodimentsaccording to the invention, the polymer insulating layer 130 has athickness of about 1 to 2 microns and a position that is spaced apartfrom within the protruding portion of the conductive via 105. In someembodiments according to the invention, the polymer insulating layer 130has a viscosity of about 290 cP, and a resistivity of about 10 to the10-ohm-cm and modules of about 1 GPa to about 3 GPa.

In some embodiments according to the invention, the conductiveprotective layer 115 can be a metal that forms in inter-metalliccompound with solder that can be used to electrically connect the TSVstructure 100 to another TSV structure stacked on. In some embodimentsaccording to the invention the conductive protective layer 115 can be ametal having a wet ability with solder that is greater than that of Td,Ti, TiM, Ta, and TaN. In some embodiments according to the invention,the conductive protective layer 115 can be Ni, and/or Co doped with arare earth element or transition metal. In some embodiments according tothe invention, the conductive protective layer 115 can be Ni doped withV and/or P or can be Co doped with W, P, Cr, and/or B.

In some embodiments according to the invention, the conductiveprotective layer 115 can be a metal having diffusivity into Si that isless than that of Au, Cu, and Ag into Si. Some exemplary metalsaccording to the present invention are illustrated, for example, in FIG.6.

In some embodiments according to the invention, the protruding portionof the conductive via 115 can protrude from the back side surface 112 byabout 15 microns and can have a total height (i.e., from the portions ofthe conductive via 105 located on the upper surface 111 to theprotruding portion) of about 45 microns and have a width of about 30microns where the thickness of the substrate 110 is about 30 microns.Although not shown in FIG. 1, in some embodiments according to theinvention, the conductive via 105 can be formed on a conductive padlocated in the substrate 110 just beneath the portion of the conductivevia 105 located on the upper surface 111. In still other embodimentsaccording to the invention, the conductive via 105 can be formed offsetfrom the conductive pad such that the conductive pad is located on theupper surface 111 spaced apart from the conductive via 105.

FIG. 2 is a flow chart that illustrates methods of forming TSVstructures in some embodiments according to the invention. According toFIG. 2 a hole is formed in a substrate (Block 505) and an insulator,diffusion barrier layer and conductive protective layer are formed on asubstrate and in the hole (Block 210).

A conductive material is formed in the hole (Block 515), and the backside surface of the substrate is processed to expose the diffusionbarrier layer, conductive protective layer on the back side of thesubstrate to provide a TSV structure (Block 220).

A polymer insulating layer is formed on the back side surface of thesubstrate and on the back side portion of the TSV structure (Block 225)and a portion of the polymer insulating layer is removed to expose theTSV structure on the back side surface (Block 330).

FIGS. 3-5 and 7-9 are cross sectional views that illustrate methods offorming TSV structures in some embodiments according to the invention.According to FIG. 3, a substrate 11 includes an upper surface 11F and aback side surface 11B and includes circuits from therein. Further, aninsulating layer 15 is formed on the upper surface 11F to have hole 15Htherein that exposes an electrical interconnect 13 that lies within theredistribution region in which a redistributed contact pad will beformed offset from the TSV structure formed in the substrate 11. In someembodiments according to the invention the interconnect 13 can be Cu,Al, W, Ti, Ta, which can be used to provide the contact pad. In someembodiments according to the invention, the insulating layer 15 can be apassivation layer formed of Si, O, Si, N, and/or Si ON.

According to FIG. 4, a recess 20 is formed in the substrate 11 using dryetching or laser drilling. In some embodiments according to theinvention, the recess 20 has a diameter of about 30 microns and a depthof about 30 to about 100 microns.

According to FIG. 5, an insulator layer 21 can be formed in the recess20 and on the upper surface 11F. In some embodiments according to theinvention, the insulator 21 is not deposited in or is removed from theopening 15H. A diffusion barrier layer 23 can be formed in the recess 20on the insulator layer 21 as well as on the upper surface 11F. In someembodiments according to the invention, the diffusion barrier layer 23can be Ti, TiN, TaN. In some embodiments according to the invention, thediffusion barrier layer 23 is also not deposited or is removed from theopening 15H wherein the contact pad will be formed. A conductiveprotective layer 24 is formed inside the recess 20 and on the uppersurface 11F including in the opening 15H. In some embodiments accordingto the invention, the insulating layer 21 and diffusion barrier layercan be combined in a single layer having the properties of both. It willbe further understood that the conductive protective layer 24 describedabove in reference to FIG. 5 can have the same properties as describedabove in reference to FIGS. 1 and 6.

According to FIG. 7, a photo resist pattern 32 is formed on theconductive protective layer 24 so that an opening in the photo resistpattern 32 exposes the recess 20 and a portion of the upper surface 11that includes the redistribution area including the contact pad.

According to FIG. 8, a conductive material 25 is formed on the recess 20and on the upper surface 11F. In some embodiments according to theinvention, the conductive material can be Cu, W, Al, which is formedusing electroless plating, CVD, or PVD.

According to FIG. 9, the conductive material 25 can be used as a hardmask to remove the photo resist pattern 32 as well as portions of theconductive protective layer 24 and the diffusion barrier layer 23 layingbeneath the photo resist pattern 32. Further, a groove 27S can be formedin the conductive material 33 that is self aligned to the center of therecess 20. In some embodiments according to the invention, a bottom ofthe groove of 27S can extend to a level into the recess that is beneatha level of the upper surface 11F by a distance d1. As further shown inFIG. 9, formation of the conductive material 25 in the recess 20 and onthe redistributed pad can provide for the formation of a redistributionpattern 27E wherein the conductive material 25 is electrically connectedto the interconnect 13 and the substrate 11.

FIGS. 10-12 are cross sectional views that illustrate the formation ofthe conductive material 27 in the recess 20 and on the upper surface 11Faccording to other embodiments according to the invention.

According to FIG. 10, a photo resist pattern 32 is formed in the recess20 and on the redistribution region including over the whole 15H.According to FIG. 11, the photo resist pattern 32 is used as an etchmask to remove the materials on the upper surface 11F located outsidethe photo resist pattern 32 to provide for the formation of the recess20 and to expose a portion of the upper surface 11F including theredistribution region.

According to FIG. 12, the conductive material 27 is formed in the recess20 and on the portions of the upper surface 11F on which on theconductive protective layer 24 remains. Accordingly, the conductive viacan be formed in the recess along with the electrical connection to theinter connect 13 for the processing as described below.

FIGS. 13-16 are cross sectional views that illustrate formation of TSVstructures by processing the back side surface 11B of the substrate 11in some embodiments according to the invention. According to FIG. 13,the back side surface 11B is processed using grinding or a chemicalpolicy process to reduce the thickness of the substrate 11 but stillavoids the exposure of a bottom portion 27B of the conductive protectivelayer 24.

According to FIG. 14, a dry etch process is used to expose the bottomportion 24B of the conductive protective layer 24, which includes aprotruding portion 25, which protrudes from the reduced back sidesurface 11B of the substrate 11. As further shown in FIG. 14, a portionof the insulator layer 21 and an underlying portion of the diffusionbarrier layer 23 are removed where the protruding portion occurs.

According to FIG. 15, a polymer insulating layer 31 is formed on theback side surface 11B including on the protruding portion of the via andparticularly on the conductive protective layer 24. In some embodimentsaccording to the invention, the polymer insulating layer 31 is appliedto the back side surface 11B using a spin coating or a spraying methodand, further, the polymer insulating layer can have an etch selectivityrelative to the conductive protective layer 24. It will be understoodthat the polymer insulating layer 31 can help relieve stress caused bymaterials that are formed on or in the substrate to reduce the tendencyof the substrate to warp. Accordingly, because the polymer insulatinglayer 31 is coated on to the back side surface 11B, the polymerinsulating layer 31 can be a separate layer distinct from the substrate11.

According to FIG. 16, the polymer insulating layer 31 is etched back toreduce the thickness thereof and the backside surface 11B as well as toexpose the conductive protective layer through the polymer insulatinglayer 31. Furthermore, the etch back process can provide the polymerinsulating layer 31 to have an incline profile at a point where thepolymer insulating layer contacts the conductive protective layer 24. Asshown in FIG. 16, the etch back process reduces the thickness of thepolymer insulating layer 31 to a thickness D2 which is less than thedistance which the protruding portion of the via protrudes from the backside surface 11B so that the protruding portion of the via protrudesthrough the polymer insulating layer 31. Furthermore, as shown in FIG.10, in some embodiments according to the invention, a thickness D3 ofthe polymer insulating layer 31 on a side wall of the conductiveprotective layer 24 included in the protruding portion thereof is lessthan the thickness D2 of the polymer insulating layer 31 on the backside surface 11B. It will be further understood that the thickness D3can be controlled by adjusting the viscosity of the polymer used to formthe polymer insulating layer 31.

FIG. 17 is a cross sectional view that illustrates a TSV structureco-located with a contact pad 13′ having portions located in thesubstrate 11 as shown.

FIG. 18 is a cross sectional view is a view that illustrates TSVstructures wherein an upper surface 27E′ of the conductive via isplainer and does not include a groove 20.

FIGS. 19-22 are cross sectional views that illustrate methods of forminga TSV structure in some embodiments according to the invention.According to FIG. 19, an insulator layer 21, diffusion barrier layer 23,and a conductive protective layer 24 are formed in the recess 20 and onthe upper surface 11F of the substrate 11 as described above. Accordingto FIG. 20, a photo resist mask 35 is formed partially in the recess 20as well as on the upper surface 11F of the substrate 11. In particular,a central portion of the recess 20 is left exposed by the photo resistpattern 35 that covers remaining portions of the recess 20 as well asthose portions of the conductive protective 24 layer outside the recess.

According to FIG. 21, the etching step is conducted using the photoresist pattern 35 to remove a portion of the conductive protective layer24 located at the bottom of recess 20, which is exposed by the photoresist pattern 35. Subsequently, the photo resist pattern 35 is removed.Accordingly, the insulator layer 21 and the diffusion barrier layer 23of the only remaining portions of the layers located at the bottom ofthe recess at region B.

According to FIG. 22, a conductive material 25 is formed in the recess20 as well as on the upper surface 11F from the substrate 11 includingon the redistribution region to provide the contact pad as describedabove. It will be understood that the conductive material 25 depositedin the recess can be patterned to provide the TSV structure according toany of the approaches described herein.

FIG. 23 is the cross sectional schematic view of a package 118 includinga three dimensional stack of substrate 121-128 connected to one anotherby TSV structures 27 on a substrate 110. It will be further understoodthat the three dimensional stack can include a substrate 129 includinglogic devices also connected to the 3-D stack using TSV structures insome embodiments according to the invention. Further, the package 118can be conducted to other devices or a substrate by solder bumps 111. Asfurther shown in FIG. 23, the substrate 110 can include interconnect 113used to provide signals to-from the three dimensional stacks ofsubstrates and the solder bumps 111.

FIG. 24 is a cross sectional view that illustrates TSV structuresincluded in the three dimensional stack of substrates and the package118 highlighted at region E1 shown in FIG. 23 in some embodimentsaccording to the invention. According to FIG. 24, the groove in theupper surface of the conductive material includes solder 33 which isused to electrically connect the underlying TSV structure to another TSVstructure located directly above the groove. It will be understood thatthe solder 33 is limited to being within the groove and does not extendon to the upper surface of the conductive material.

FIG. 25 is a cross sectional view that illustrates alternativeembodiments of interconnected TSV structures included in the package 118shown in FIG. 23 in some embodiments according to the invention. Inparticular, solder 33′ used to interconnect the two immediately adjacentTSV structures is not limited to within the groove and rather extends onto at least a portion of the upper surface of the conductive materialused to form the lower TSV structure.

FIG. 26 is cross sectional view that illustrates a conventionalstructure wherein a solder 34 used to electrically connect the upper andlower TSV structures may provide additional thickness D4 to the overallheight of the three dimensional stack.

FIG. 27 is a cross sectional schematic view that illustrate a threedimensional stack of substrates including TSV structures used forelectrical connections between the three dimensionally stackedsubstrates. In particular, the TSV structures can be configured with theredistributed region including the pads which can be electricallycoupled to TSV structures located in the immediately adjacent substratesin the three dimensional stack. Furthermore, the redistribution regionsand TSV structures associated therewith can be arranged to make zigzagpattern as shown. It will be understood that the arrangement shown inFIG. 27 can be utilized to provide a three dimensional stack ofsubstrates including memory devices as well as a logic chip 139 locatedwithin the three dimensional stack.

FIG. 28 is a cross sectional schematic view of a package 118 which wouldinclude the three dimensional stack of substrate electrically connectedto one another by TSV structures in some embodiments according to theinvention. In contrast, the two embodiments illustrated in FIG. 27, thearrangement illustrated in FIG. 28 provide parallel interconnection ofthe TSV structures utilizing the contact pad located within the TSVstructures rather than offset therefrom as shown in FIG. 27.Furthermore, as shown in FIG. 28 the three dimensional stack ofsubstrates can be used to implement memory devices within the packagewhich may also exclude a logic device 139 in comparison to that shown inFIG. 27.

FIG. 29 is a cross sectional schematic view that illustrates a threedimensional stack of substrates electrically interconnected with oneanother using TSV structures in some embodiments according to theinvention. As further shown in FIG. 29, a logic chip 159 can be includedwithin the three dimensional stack of substrates. As further illustratedin FIG. 29, the TSV structures can be coupled to one another using aninverted TSV structure.

FIG. 30 is a cross sectional view that illustrates the adjacent TSVstructures within the three dimensional stack of substrates shown atregion E1 in FIG. 29. According to FIG. 30, solder 33 located in thegroove of the upper TSV structure is fully confined therein and does notextend out of the groove.

FIG. 32 is a cross sectional schematic representation of a package 118including a three dimensional stack of substrate electrically connectedto one another by TSV structures arranged in a zigzag pattern in someembodiments according to the invention.

FIG. 33 is a plan view of a memory card formatted to a standardform-factor card including non-volatile memory, controller chip 195, andexternal terminals 193 used to interconnect the memory card to a socketin some embodiments according to the invention.

FIG. 34 is a cross sectional schematic view along cross section I-I′shown in FIG. 33 in some embodiments according to the invention. Inparticular, a substrate within the card 199 includes interconnect 192that is connected to the external terminals 193. The interconnect 192also electrically connects to substrates for the controller chip 195 aswell as the substrates within the three dimensional stack of substratesused to implement the non-volatile memory within the memory card.According to FIG. 34, both the controller chip 195 and the substrateswithin the three dimensional stack used to implement the non-volatilememory are electrically connected to one another using TSV structureswhere the contact pads are included within the TSV structures themselvesas illustrated above, for example, in FIG. 17.

FIG. 35 is a plan view of a non-volatile memory implemented according toa standard form factor including a non-volatile memory 198 and externalterminals 193 in some embodiments according to the invention.

FIG. 36 is a cross sectional schematic view along cross section II-IIprime shown in FIG. 35. According to FIG. 36, a three dimensional stackof substrates is used to implement the non-volatile memory 198 andfurther can include a substrate 195 prime used to implement thecontroller. Further, the substrate 191 prime includes electricalinterconnect 192 that is used to electrically connect the externalterminals 193 to the substrates within the three dimensional stack.Furthermore, the three dimensional stack substrates are interconnectedby TSV structures having contact pads formed therein as shown forexample above in FIG. 17.

FIG. 37 is a schematic representation of a memory module includingpackages 207 including memory devices on a substrate 201 wherein IOterminals 205 are used to connect the memories within the packages 207to devices located outside the memory module. Furthermore, the memorymodule can include a controller unit 203 to coordinate operations of thememory devices included on the module. It will be understood that memorydevices included within the packages 207 can be formed with TSVstructures as described herein in some embodiments according to theinvention.

FIG. 38 is a block diagram of an electronic system that includes aprocessor 215 coupled to a memory 217 and an IO device 213 by a bus 219.It will be understood that the devices used to implement the processor215, the memory devices 217 and the IR devices 213 can all beimplemented using TSV structures in some embodiments according to theinvention.

Many alterations and modifications may be made by those having ordinaryskill in the art, given the benefit of present disclosure, withoutdeparting from the spirit and scope of the invention. Therefore, it mustbe understood that the illustrated embodiments have been set forth onlyfor the purposes of example, and that it should not be taken as limitingthe invention as defined by the following claims. The following claimsare, therefore, to be read to include not only the combination ofelements which are literally set forth but all equivalent elements forperforming substantially the same function in substantially the same wayto obtain substantially the same result. The claims are thus to beunderstood to include what is specifically illustrated and describedabove, what is conceptually equivalent, and also what incorporates theessential idea of the invention.

1. A method of forming a Through-Silicon-Via (TSV) comprising: forming aconductive via through a substrate extending from an upper surface ofthe substrate to a backside surface of the substrate, opposite the uppersurface, having a conductive protective layer comprising Ni and/or Coformed at a bottom of the conductive via; and forming a polymerinsulating layer on the backside surface that is separate from thesubstrate and in contact with the conductive protective layer.
 2. Amethod according to claim 1 wherein forming a conductive via furthercomprises: forming a recess in the substrate, the recess having anopening on the upper surface of the substrate; forming the conductiveprotective layer at the bottom of the recess; depositing a conductivematerial on the conductive protective layer in the recess; andprocessing the backside of the substrate to provide a protruding portionof the conductive material and the conductive protective layerprotruding from the backside surface.
 3. A method according to claim 2further comprising: forming a groove in an upper surface of theconductive material having an opening facing away from the substrate andconfigured to extend into the via to beneath the upper surface of thesubstrate.
 4. A method according to claim 3 further comprising: formingsolder in the groove; and electrically connecting the solder to anotherTSV structure above the conductive via.
 5. A method according to claim 2further comprising: forming solder on a planar upper surface of theconductive material; and electrically connecting the solder to anotherTSV structure above the conductive via.
 6. A method according to claim 1wherein the polymer insulating layer has a viscosity comprising about290 cP, a resistivity of about 1010 ohm-cm, and a modulus of about 1 GPato about 3 GPa.
 7. A method of forming a Through-Silicon-Via (TSV)comprising: forming a recess in a substrate having an opening on anupper surface of the substrate; forming a conductive protective layer ata bottom of the recess; depositing a conductive material on theconductive protective layer in the recess; processing a backside surfaceof the substrate, opposite the upper surface, to provide a protrudingportion of the conductive material and the conductive protective layerprotruding from the backside surface; and coating the protruding portionand the substrate with a polymer insulating layer to a thickness ofabout 1 to about 2 micrometers at a first location spaced apart fromwhere the protruding portion protrudes from the backside surface and athickness of about 8 micrometers at a second location at the protrudingportion measured relative to the backside surface.
 8. A method accordingto claim 7 wherein the conductive protective layer comprises Ni and/orCo.
 9. A method of forming a Through-Silicon-Via (TSV) comprising:forming a recess in a substrate having an opening on an upper surface ofthe substrate; forming an insulator layer, a diffusion barrier layer,and a conductive protective layer comprising Ni and/or Co, at a bottomof the recess and on the upper surface; forming a photo-resist patternincluding an opening on the upper surface exposing the recess;depositing a conductive material in the recess through the opening;processing the upper surface to remove the photo-resist pattern andportions of the conductive protective layer and the diffusion barrierlayer beneath the photo-resist pattern; processing a backside surface ofthe substrate, opposite the upper surface, to provide a protrudingportion of the conductive material and the conductive protective layerprotruding from the backside surface; coating the protruding portionwith a polymer insulating layer that is separate from the substrate; andremoving a portion of the polymer insulating layer to expose theprotruding portion.
 10. A method according to claim 9 wherein processingfurther comprises: processing the backside surface using grinding orchemical-mechanical-polishing (CMP) to reduce a thickness of thesubstrate to provide a reduced backside surface and to avoid exposingthe conductive protective layer; and then dry-etching the reducedbackside surface to further thin the substrate and to expose theconductive protective layer.
 11. A method of forming aThrough-Silicon-Via (TSV) comprising: forming a recess in a substratehaving an opening on an upper surface of the substrate; forming aninsulator layer, a conductive protective layer comprising Ni and/or Co,and a diffusion barrier layer at a bottom of the recess and on the uppersurface; forming a photo-resist pattern including an opening on theupper surface exposing a central portion of the bottom of the recess andcovering an outer portion of the bottom of the recess; processing theupper surface to remove a portion of the barrier layer in the opening toexpose an underlying portion of the conductive protective layer;depositing a conductive material in the recess through the opening;processing a backside surface of the substrate, opposite the uppersurface, to provide a protruding portion of the conductive material andthe conductive protective layer protruding from the backside surface;coating the protruding portion with a polymer insulating layer that isseparate from the substrate; and removing a portion of the polymerinsulating layer to expose the protruding portion
 12. A method accordingto claim 11 wherein processing further comprises: processing thebackside surface using grinding or chemical-mechanical-polishing (CMP)to reduce a thickness of the substrate to provide a reduced backsidesurface and to avoid exposing the conductive protective layer; and thendry-etching the reduced backside surface to further thin the substrateand to expose the conductive protective layer.
 13. A method of forming aThrough-Silicon-Via (TSV) comprising: forming a recess in a substratehaving an opening on an upper surface of the substrate; forming aninsulator layer, a diffusion barrier layer, and a conductive protectivelayer comprising Ni and/or Co, at a bottom of the recess and on theupper surface; forming a photo-resist pattern in the recess and outsidethe recess so that a portion of the insulator layer, the diffusionbarrier layer, and the conductive protective layer outside the recess isexposed; etching the portion of the insulator layer, the diffusionbarrier layer, and the conductive protective layer outside the recess toremove the portion; removing the photo-resist pattern; depositing aconductive material in the recess; processing a backside surface of thesubstrate, opposite the upper surface, to provide a protruding portionof the conductive material and the conductive protective layerprotruding from the backside surface; coating the protruding portionwith a polymer insulating layer that is separate from the substrate; andremoving a portion of the polymer insulating layer to expose theprotruding portion.
 14. A method according to claim 9 wherein processingfurther comprises: processing the backside surface using grinding orchemical-mechanical-polishing (CMP) to reduce a thickness of thesubstrate to provide a reduced backside surface and to avoid exposingthe conductive protective layer; and then dry-etching the reducedbackside surface to further thin the substrate and to expose theconductive protective layer.